The following material is licensed under Creative Commons Attribution-NonCommercial-ShareAlike (CC BY-NC-SA 3.0) license. Basically, you are free to remix, tweak, and build upon my work non-commercially, as long as you credit the original work properly and license your new creations under the identical terms. You have, to, however, ask my permission if you are planning to use the material or inherited works commercially.

Please note, that this is all preliminary and evolving, but as it is work in progress perhaps somebody will find something useful here meanwhile.

    Basics of SDR
    SDR Architectures
        Basic with digital sound
        Full Digital
    SDR Mark1

    Christophe F4DAN SDR Page
        Classifying SDR Projects
    PA3FWM's SDR Page
    SDR RF Front End Topologies

January 6, 2011


The quest for the Software Defined Radio, or SDR for short,  started shortly after this website was set up. I wanted to free my trusted Icom IC-R20 from its duty of feeding the UVB-76 buzzer to the soundcard and wanted something what would do the same for me, but would be inexpensive and compact at the same time. 
What I ended up with was a nifty little SDR receiver Soft66Lite from what surprisingly met all these requirements for a less than $20 as a kit.

While being great for just receiving one single station 24/7 with a tolerable quality, it soon become apparent, that if I wanted to push the concept of the website from being just a dumb relay to something more advanced, somewhere along the ideas of where has started to move, I do need something way more powerful than Soft66.

I have admired the work of the Pieter-Tjerk de Boer, (PA3WFM) the creator of the WebSDR concept, ever since I visited his site the first time. For running the website he has developed his own fully digital SDR, the development of which is described at his page. I wanted to create something similar, but slightly different. 
The new powerhouse for this site is actually coming to be what I call SDR Project MK2. During the process of designing it, I did, however, that although there are plenty of SDR designs in the net, most pf them are relatively old and do not benefit from the wonders of where the communications industry has gone thanx to semiconductor development. 

So, why not design something what the members of the UVB-76 community could afford, yet something what would be state of the art year 2011 design of the shortwave SDR receiver. And so the idea for SDR Mark1 was born.

Basics of the SDR

In order to put things in perspective, a little tutorial about the SDR receivers is due. What really makes the SDR so special and different from the ordinary superhet or direct conversion receiver?

It is really simple - the difference between SDR and ordinary radio receiver is, that at some point, between the antenna and listener, the signal is converted from analog to digital and the rest of the operations, whatever has to happen to the signal, is performed digitally. The only major difference between different breeds of SDR receivers is how close to the antenna the signal is converted to digital form. Don't get it wrong - it does not have to happen very close to the antenna at all! Most SDR designs from mid-2000 are actually nowhere near the radio frequencies at all, but rather use the simple direct conversion receivers to get from RF to lower frequencies, then feeding it to the sound card and use computer software to decode audio signals from the already relatively low-frequency signals.

Let me introduce you some of the basic SDR architectures

SDR Architectures

There is an excellent page from Christophe f4dan at He has been trying to classify the SDR receivers by the architecture used and also has a great collection of different designs listed from all around the Internet. He has been going really in-deep with the technical aspects of the design classification a , I am taking somewhat simpler path here, using only the criteria as "where the analog turns digital" as a classification.


The basic design consist of direct conversion receiver what receives the RF frequency, down converting it with simple RF mixer making it therefore a simple direct conversion receiver. This down converted signal (which is inherently a 0MHz IF frequency) is fed to sound card, where it is decoded for the desired modulation, will it be AM, FM, SSB or some sort of digital processing.

The following two drawings are actually taken from the excellent but very technical article RF Receiver Front End Topologies for SDR, written by Jeffery H. Reed at Virginia Tech.

If you want to know more in-depth about what and how, please read his article, I am keeping it more of the popular science.

Dependent on how the frequency down conversion is done, it can be either simple one-channel audio signal of a combination of two signals, typically labeled as I and Q. The combination of the I and Q signals allow the software to decide, if the particular frequency appearing in the signal was actually xxx Hz higher or lower from the base frequency we used to down convert from, allowing therefore twice the width of the bandwidth. (This does sound complicated, I know. But to explain it takes another page full of text, so I leave it here and you can google what it really means).

The upside of this approach is, that it gives you really simple and straightforward SDR design, allowing to construct a very simple receivers. This is what the UVB-76 site uses for receiving on 4.625MHz and there are several designs around what are even simpler. The nice example is at what can only be described as a vacuum tube SDR receiver!

[here be table]

Note, that SDR receiver can or can not be tuned from the computer. One can certainly tune within the range of the bandwidth provided by the sound card. On typical 48kHz sample rate sound card one can tune from 0 to +24kHz from center frequency if only one channel of audio is available, and -24kHz to +24kHz if both, I and Q are available. For example, if you will center your receiving frequency on 7050kHz, you can tune your radio from 7026kHz to 7074kHz if you have I and Q signals available to your sound card, without having to touch the SDR hardware itself!. However, on most of the basic SDR receivers have their center frequency fixed, so there is no way to receive on 7000kHz with the mentioned receiver without tuning the board manually.
More expensive designs do have capabilities for tuning the receiver center frequency, but the need for several different filter blocks will start escalating the price quite fast.

Most of the SDR receivers do require computer software in order to decode the signal coming from SDR to be audible. 
There are several different programs for doing that, although about 4-5 stand out and are widely used by SDR listeners

[here be table]

If one wants to listen to digital broadcasts what provide sound quality close to FM radio stations, one needs different program.

[here be table]

Basic with digital sound

This is technically very close to previous design approach, but has a (normally USB) audio chip designed on-board.
This will serve two purposes: first, the incorporated sound card can be well matched with the design by signal level and other features, so it provides better signal to noise ratio and image rejection. The other benefit is, that there are USB audio chips available today providing 192kHz bandwidth quite inexpensively, so on the previous example we could get the tuning capabilities from 6858kHz to 7242kHz which is quite significant improvement.
Note, that the data between computer and SDR board is now already traveling in digital form, so it is not prone to interferences any more. The data can be transmitted either with USB, Ethernet or some other way, such as SP/DIF.

The rest of the processing is the same as for the basic direct conversion model and the RF front end is with the similar structure, consisting of RF mixer and oscillator which frequency can or can not be controlled from the PC software.

Full digital design 

This is the third large category of SDR receivers and this is what makes "The Real SDR". It is the whole nature of the SDR design to push the ADC (analog to digital converter) as close to the antenna as possible and the ultimate goal is to plug the antenna directly to the ADC chip.

This is where world has really advanced in past 2-3 years, as the fast ADC chips have finally become affordable.
Why we do need a fast ADC chips is, that if we do want to, for example, digitize the incoming 7MHz radio signal, we need a sampling rate of at least twice of that frequency, what meas that we must have a ADC chip what is capable of 14MSPS (megasamples per second) data rate. For a comparison, your average computer sound card has a capability to sample audio with 48KSPS, which is 296 times slower ...
There are possibilities to use slower ADC's and use a second Nyquist zone for sampling, but the filtering of the incoming signal nullifies some of the benefits of putting ADC close to antenna.

However, today we can have 40MSPS ADC available for $30, so this is more than satisfactory for building a decent shortwave receiver.

Note, that despite putting the ADC close to antenna and sapling the entire RF band at once, we still need to go through all the necessary steps in signal processing, much like for the basic type of receiver, The difference is, that all of this is happening now in digital domain, therefore eliminating most of the problems associated with analog noises and artifacts. We still have to perform the signal down conversion from base frequency and decode it for AM, FM, SSB etc. There are several possibilities for doing that: we can take a really fast computer and transmit the entire data feed to computer using USB 2.0 or Ethernet. We can then process it by software, although it is takes large bandwidth and lot of processing power. We can use digital down converter (DDC) chips connected to ADC and have them perform a down conversion for us. The resulting, now much  lower-bandwidth feed, can be then transferred to computer and processed as audio stream on the basic SDR case. The most complicated, but also the most flexible way of doing it would be doing the signal processing using a programmable logic devices, such as FPGA-s. These are basically a software-configurable hardware parts, so one can design a logic circuits, upload the resulting design much as a computer software to the chip and chip starts to behave particular way as the software tells him. The design can be modified as needed within the chip and additional processing can be added. 
We still have to go through all the steps in signal conversion tho and then feed the resulting digital signal to computer or some other converter what creates audio signal for us.

[here be table]

The SDR Mark2 for site is using the latter architecture. The SDR Mark1 presented here is using the dedicated DDC chip approach. 

But this is as far as I want to go with explaining the world of SDR receivers - let us build one!


National Semiconductor (NSC) has created a perfect chip for building the SDR, named LM97593. It accommodates all of the building blocks needed for building a SDR in one housing: It has 70MSPS ADC and it has DDC chip connected to it, so we can connect it directly to the antenna and have already downsampled digital audio signal coming out. And it has two of such channels, whatever its good for on our case. Even better, it has built-in gain control, so if used together with DVGA (variable gain amplifier) amplifiers, such as NSC's own LM6515, we do have RF gain automatically controlled! 
The only downside of this chip is, that at the moment of writing this article, it seems that only 90 pieces are around the whole world, so its availability is not as good as I would wish. NSC was, however, able to send me the samples promptly. In order to get the data from chip to computer and provide necessary control signals to the chip we need something what would connect to the computer with high speed and have some computing power in it. 
The initial platform of choice for me became the CY7C68013A microcontroller from Cypress (also known as EZ-USB FX2LP) driven by the hopes for making the SDR MK1 compatible with GnuRadio project. However, after playing around with the FX2LP development kit I decided to abandon the Cypress in favor of Atmel AT90USB1287 what has better accessible toolset in form of AVR Studio 4 and WinAVR, not to mention the excellent LUFA (Lightweight USB Framework for AVRs, formerly known as MyUSB) framework. For programming the chip through the USB interface you are also going to need to download FLIP (Flexible-in-system-programmer) from Atmel.
The full story about Cypress vs. Atmel can be found in blog HERE.


The schematic for V1.0 of the SDR MK1 is following. Please note, that this is untested/prototyped/verified design, so if you are using this as a reference to something else, please take it with great care. I have not been able to find reference design or evaluation board schematic for LM97593 so it is somewhat shot in the dark, but we will get to know soon.

This design satisfies several requirements what I have set for the successful SDR project:
  • It has to be fully digital, with the ADC connected as close to the antenna as reasonable.
  • It has to be possible to build on 2-layer board and if everything else falls apart, one should be able to build it using photoresist technology in his own kitchen. However, as I have not yet done PCB layout at the moment, I will reserve a right to withdraw this and sell you a bare PCB board should it become 4-layer!  :)
  • It should contain no BGA (ball grid array) footprint components (it sadly contains two small LLP packages what are rather difficult to put on board without a reflow owen, but they have small number of connections, so it is still doable with just a soldering iron)
  • Avoid FPGA for interfacing
  • It should be compatible with already existing SDR software
  • It shall cost around $100.

Well, with the exception of the price, all the requirements are met. The component cost is about $150, not counting the PCB. The PCB cost is around $20 in small quantities, so we are still below $200 which is pretty good result. However, for this $200 it will be equal if not better to any shortwave receiver 10x this price range.
The design itself looks more complicated than it really is, as the component count is relatively large because of large number of different power supply paths what have their individual decoupling/filter capacitors and inductors. As the LM97593 chip has also two separate ADC inputs, I have implemented two separate frontends with applicable lowpass filters, what increases component count significantly while being just a copies of each-other.

The input of the SDR is based on two LMH6514 DVGA (Digital Variable Gain Amplifier) chips from National Semiconductor. This is more or less off from the reference schematics and provides a RF amplifier what gain can be adjusted from 0 ..42dB.
The input of this chip is fed through the transformer, what serves two purposes: DC isolating the antenna from the rest of the radio (and your computer connected via USB interface) and matching the asymmetrical 50 Ohm asymmetrical antenna to a 200 Ohm symmetrical input of the LMH6514.
In order to have a good design, we have to add a low-pass filter before the ADC chip. This makes the schematic more complicated than it really is, but without the filter we are going to see ghost images of higher frequencies than half of our sample rate. This will garbage the frequency spectrum, therefore we have to filter.

The filter is a classic Chebyshev 7-pole low-pass filter adapted for symmetrical signal path. The output impedance of the LMH6514 is adjusted with 400 Ohm resistors R6 and R9 to equal 150 Ohm for no better reason than the fact that 150 Ohm gives us inductor and capacitor values close to values what an be found among standard components. The other end of the filter is also terminated with 150 Ohm resistors for the very same reason.

The calculated filter (Calculator can be found at has somewhat different capacitor values than those found on schematic. The original values were 47/2pF, 82/2pF, 82/2pF and 47/2pF.

This results with the following simulated characteristics of the filter:

However, with the values found on the actual v1.0 schematic, the simulation looks following:

With 1.4dB ripple which is not very significant, we are getting much steeper cutoff at 32MHz what results much better image rejection. Also, the slight bump just before 32MHz contributes slightly.
The actual filter performance is of course dependent on components used, but with 1-2% tolerance in nominals it will look close enough.
Note, that inductors and capacitors preceding the filter are not actually part of the filter itself. Two inductors L4 and L5, tied to positive power rail, are used to bias the LMH6514 output stage. The capacitors C9 and C21 are there to DC-isolate the input stage of LM97593, as it requires different bias.

The inductor and capacitor values are chosen so that they will not affect low-end performance of the filter too severely. The simulated filter performance at kHz range is following:

As seen from graph, the SDR MK1 is not exactly suitable for VLF experiments on extreme, but it is totally adequate for receiving the Alexander - Grimeton alternator on 17.2kHz whenever it transmits!

The LMH6514 DVGA chip goes almost to 1GHz and so does the LM97593 tuner, as both are dedicated for GSM industry. Therefore SDR MK1 is theoretically capable of receiving up to a GHz band if the lowpass filter is replaced with appropriate bandpass filter. The DVGA output impedance has to be lowered to around 50 Ohm on that case (see LMH6514 datasheet for details). The actual bandwidth is still limited to 30MHz, so its not going to be a wideband scanner, but it can be used for monitoring higher amateur frequencys close to 1GHz this way. There are testpoints on board for connecting custom filter board(s). The existing filters have to be removed of course!
Please also note that with quite simple external mixer one can easily go above GHz if desired!

The LM97593 ADC/DDC/Tuner chip is a workhorse of the entire project and this is what is often implemented on FPGA in modern SDR projects. FPGA approach is good if you want to experiment, but its a rather long experiment and you have to get familiar with many aspects of digital signal processing before you can succeed. I have started to teach myself on that and my next SDR will be based on FPGA as a learning project in case National Semiconductor decides to cancel producing the wonderful LM97593, but so far the dedicated chip is both, better and more cost-effective.
One thing I have to point out is a strange power scheme used for all the chips - most of the stuff you see normally operated on 3.3V is fed with 4.0V power bus. This is mainly originating from the reason, that Atmel AT90USB1287 chip we are using for interfacing is able to run only up to 8MHz if run on 3.3V power supply. To gain the 16MHz performance, it requires 4.5V supply minimum.
The LM97593 on the other hand is only allowed to run up to 4.2V. So if we boost the Atmel power to +5V, all the I/O of the LM97593 are driven above the spec, and this will degrade the chip over time. Putting the level converters between signals was too bulky solution and 8MHz processor speed was feeling too slow, so I took all the components to common 4V what they all tolerated (including the DVGA input amplifiers) and compromised to a 12MHz processor clock.

All the different power paths are isolated with inductors to avoid cross-interference, especially between the analog and digital parts. We will see how well it works in reality.

The other trick with the power starts from the CPclare solid state relay just after the USB connection. As you see, the Atmel part is powered directly from the USB bus, while rest of the circuitry has its power delivered through the solid state relay and also shut down by default using the shutdown signals at the LDO (low drop-out) regulators.

The reason for this is that not all USB outputs these days are capable for delivering the 500mA output current as was the case in the past. USB spec nowadays only guarantees 100mA and anything more has to be negotiated with the USB host device on a software level. We are using an hefty 590mA on worst-case scenario and 400+ mA most of the time. Therefore only the Atmel part is powered initially and negotiations with USB host are held. Should the negotiations about 0.5A be successful, the rest of the devices are enabled. If not, then the SDR shall rely on external power supply connected or flash an error LED and do nothing.

Everything is spinning around Atmel AT90USB1287 what provides necessary USB interfacing and communication with host computer. It is providing an 44.1kHz/48kHz/192Hz 2-channel (stereo, for short) audio interface for I and Q signals coming from the digital tuner. It is also providing two serial ports, one for communicating with the receiver and other for debugging/monitoring/terminal purposes.


This is what the current (prototype)production layout (v1.02) looks like.

The PCB drawings in PDF form can be downloaded Here.

Few words about the design. The outline of the board is chosen to fit the milled aluminum box (check the blog entry to see exactly how it looks like) and the final dimensions were gauged by eye to be more or less certain everything fits on the given formfactor. Like always, it "almost did not fit", but this is the case with all the PCB layouts in the world (I am sure if I would have picked up a shoebox, it would have "exactly" fitted in there as tight ...).

Its not the easiest, nor the most complicated layout I have done, but it is tricky in a sense that it is a mixed signal design (part of it is analog, part is digital) in quite constrained space, so all the components had to be placed in their most optimal locations and only then was I able to start dealing with digital signal paths.

The layout is two layers only, and while normally you would use four layers for design like that in order to be able to produce decent power and ground planes, the only reason this one is two-layer is that "I could"! :)

I will see how the prototype behaves and if there are supply or noise problems, I will separate the power and ground. However, it finally turned out quite OK as far as I wanted to have things be, so we'll see. The overall complexity of the routing would not actually be much simpler than it is with two layers, as I did not have to "stitch" with more than 10 connections. (Meaning, that I did not have to go around the world and use excessive number of vias to get from one place to another with the signal). This holds true even for insanely dense digital bus region between the radio chip and Atmega controller. Most of the bends and reverses are caused by how the signals were laid out on the chips and I did not want to obscure the schematic (and software development therefore) by, for instance, reversing the address bus bits.

The input is isolated form the rest of the design with separate ground and transformers. There are also two surge arrestors next to BNC connectors and while these are 60 volt devices, they will not be able to save the DVGA amplifiers, but will hopefully stop the high voltage spreading around the board and save your computer when lightning hits the antenna (knock the wood).

The DVGA and filter part are kept symmetrical for both channels and have testpoints around, so other filter boards can be connected. There is no ground plane below the filters as NSC datasheet suggests.

The analog input circuitry is connected to the radio chip in a way I am not really satisfied, but I want to see how its working in reality. Normally you would place these tracks between ground planes and match their impedance with the source and destination impedance. Sort of like a coaxial cable on the PCB. As this was the only place I really would have needed the four layers, I cut the corners and just routed the signals from one place to another, period. I did, however, match the length of the same channel signals to within 1mm (thus the strange zigzag at the top of the board) and used round corners as normally done on high-speed RF designs. There is certainly a certain amount of cross-talk, but don't know how much before actually seeing the board work. The digital signals running on the top layer in parallel with analog signals are the DVGA gain control bus for input amplifiers and should not have extensive traffic on them, so hopefully there is not much interference.

The capacitor and resistor mess next to radio chip is how NSC has designed it. The fact that three power buses and both channel analog inputs, together with internal analog reference support capacitors for both channels are actually at the same edge of the chip would not require a four layer, but four-sided board to make it look nice!! As there is no reference design to be found anywhere about the LM97593 chip, I have no idea how they have meant it to be look like. This is my implementation of it and hopefully a working one.

There is really not much else to the layout - the AT90USB1287 controller is connected to the radio chip directly as we have opted to a 4V power bus for both and therefore do not have need for level conversion on signals. Theoretically the design would benefit from 22 ohm resistors on all digital signals to reduce the digital noise, but that has too much impact on space. Also the traces are very short, so there is not much reactance the digital signal fronts have to encounter.

Power supply is quite straightforward and has no specialities from layout perspective. The large number of electrolytics and inductors make it look like an expensive soundcard of a sort, but then again, it is! :).
As a sidenote, yes, I know tantalum caps would have been much neater (and, perhaps, more appropriate), but I have seen so many tantalum capacitors catching fire in my life with no apparent reason, that I try to avoid using them as much as I can. The low ESR electrolytics followed by 0.1uF and 0.01uF ceramics are providing the result exactly as adequate.

What makes the layout messy is all the headers I have put on board. Theoretically, we do not need any of those. The digital data bus on top of the board can be used when  one wants to implement hardware decoder on FPGA (for digital audio, for example) of in some other reason get the raw digital IF feed out from the board. ICSP connector is needed when you manage to kill the internal bootloader of the AT90USB1287 chip during the software update. JTAG ICE connector is useful if you want do develop software and want hardware debugger functionality. The cryptic connector HWBE is a Atmega internal bootloader enable/disable jumper what you are going to need if you want to upgrade the internal software of the SDR through USB. And finally, the extension connector is for those who want to use the on-board Atmega processor for anything else besides driving the radio chip, would it be a custom front panel, antenna selector automation or something else.

The USB connector chassy ground is not directly connected to overall ground, but via large 1M resistor and 4.7nF capacitor. I did not want the USB cable shield to garbage the power (gound) bus on the board. I also did not want the metal housing of the SDR be directly connected to ground, as that would sometimes end up with unwanted encounters with other stuff laying around on the table and connected to computer on the other end.
One thing I have to see from real-life tests is how the unit behaves when large static spark is discharged to the metal housing - it should not cause reset or hanging or othe side-effects on host computer nor SDR receiver itself.


  1. Looking forward to seeing your schematic!

  2. Looks like there are several Chinese vendors with a fair quantity of the LM97593

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